One of many techniques of reducing power consumption within an integrated circuit (IC), such as a processor, is to stop or block a clock signal to a portion or to the whole of the processor. This method may require the assertion of a "stop clock" signal, upon which a processor enters a state of low power consumption (i.e. a low-power state) in which many functional units of the processor are no longer clocked. In order to maintain the performance advantages provided by cache memories associated with a processor, it is desirable that cache coherency be maintained, even when the processor is in a low-power state.
Many computer systems employ multiple processors. At any one time, one or more of these processors may be in a low-power state while others may continue to operate on data while in a fully powered state. In order to maintain cache coherency in such computer systems, the processors operating in low-power states must monitor and respond to a number of signals resulting from activity of the other processors. The powering of cache coherence and snoop circuitry necessary for responding to snoop requests resulting from the activity of other processors consumes a lot of power, and it is accordingly desirable to reduce this power consumption to a minimum when a processor enters a low-power state.